A semiconductor chip including a semiconductor device and the like is jointed to a package substrate and mounted on a printed wiring board and the like as a semiconductor package.
For Example, in a semiconductor package, a plurality of pads of the semiconductor chip and a plurality of terminals provided on prescribed positions on the package substrate are electrically connected by bonding wires, and electrically connected through wiring provided on the package substrate. Meanwhile, the terminal refers to a terminal that is provided on the joint surface of the package substrate to which the semiconductor chip is jointed, and that is connected through a via and the like via a bump (ball), a land or a pin of the package substrate used when the package substrate is jointed to the printed wiring board. Since the bump (ball), the land or the pin is provided on prescribed positions of the package substrate, the terminals mentioned above are also provided on prescribed positions on the package substrate in the same manner with the bump (ball), the land or the pin.
Such assignment for wiring of a plurality of pads of a semiconductor chip and a plurality of terminals provided on prescribed positions of a package substrate, that is, the assignment of the terminals to the pads is performed according to the design policy of the semiconductor manufacturer. Since there are a large number of combinations for the assignment according to the number of pads and the number of terminal, when the design policy is different, the assignment result is also different.
For example, a design method of a semiconductor chip has been known that optimizes the connection between input/output pads that are flip-chip jointed to a semiconductor package and the land for the bump.
In the design method, specifically, in descending order from the high rank of importance of the electrical characteristic, a pin of the package in the shortest distance from each of the input/output pads included in the rank is selected respectively. Then, according to the electrical characteristic of the wiring pattern at the semiconductor chip side and the electrical characteristic of the wiring pattern at the package side, the optimal land for the bump is arranged and selected respectively on the straight line or its vicinity that passes through each of the input/output pads and the selected pin of the package. Accordingly, a wiring pattern in which the land for the bump arranged and selected for each of the input/output pads and the input/output pads are respectively connected is designed.
Incidentally, in recent years, the integration degree of the semiconductor chip has been more and more integrated, and as the function of the semiconductor chip improves, on the pad of the semiconductor chip pad, in the assignment mentioned above, the number of pads with a high degree of importance of the electrical characteristic, that is, the number of important pads has been increasing. Now, for example, a case in which about 10% of the number of pads of a semiconductor chip are important pads for which the assignment mentioned above is performed in consideration of their electrical characteristic is assumed. For example, when the number of pads is 1000, the number of important pads is about 100. Here, the important pads whose degree of importance of electrical characteristics is high are, for example, the pad that inputs/outputs a signal with a smaller amplitude compared to the power supply voltage or a analog signal, the pad that supplies power supply voltage, the pad connected to the ground, and the like.
When the number of such important pads with high degree of importance of the electrical characteristic is increasing, in order to satisfy the constraint condition of the electrical characteristic, the terminals of the package substrate are often assigned to the vicinity of the pads of the semiconductor chip. In the known design method of the semiconductor chip mentioned above, since the assignment is performed in descending order from the pad of the high rank of importance of the electrical characteristic, the terminals of the package substrate is assigned to the vicinity of the semiconductor chip in a concentrated manner.
However, when the terminals of the package substrate are assigned in a concentrated manner to the vicinity of the pads of the semiconductor chip in consideration of important pads, for other pads with easier constraint condition of the electrical characteristics and low priority for assignment, assignment that satisfies the constraint condition may not be able to be performed. In such a case, for example, a redesign of the package substrate is to be performed manually by means such as to change the interval of terminals of the package substrate that are the target of the assignment, making it impossible to assign the terminals of the semiconductor package efficiently.